A read-only memory is generally used to store a program or data in a unchangeable manner. Such a memory is in fact programmable during a manufacturing step. The use of such a memory is highly varied. For example it is used in chip cards, microcomputers, on-board systems, etc. The main advantage of this type of memory stems essentially from the fact that it is impossible to modify the data, and also from the relatively small surface area that it takes up as compared with PROM, EPROM or EEPROM type memories.
In one application a ROM is used in particular to permanently fix the state of an ASIC using a microprogrammed system, for example of the microcontroller type, that has been developed by means of an EPROM type memory and is intended for mass production. The circuits are smaller and require fewer manufacturing steps (they have no floating gate) when they are produced with ROMs.
In the prior art, there are several known types of ROMs. They can be distinguished, for example, by the type of programming used which corresponds to the structure of a storage element. However, the description shall be limited to MOSFET type memories. Indeed, there are memories using different technologies, for example DTL or TTL technologies, which, however, are not compatible with very highly integrated, low-consumption MOS type circuits.
There are "active level" type ROMs. These storage elements include a transistor represented schematically in FIGS. 1a and 1b. Each of the figures illustrates a possible state of a bit to be memorized. Naturally, the state of the bit is arbitrary and depends on all that is placed between the transistor forming a storage element and the output of the memory. FIG. 1a shows a transistor 1 that has a source connected to the ground, a gate connected to a control line 2 and a drain connected to a bit line 3. When it is desired to select this storage element, the control line 2 is positioned at a positive voltage greater than the threshold voltage of a MOS transistor and the bit line 3 gets connected to the ground by means of the transistor 1. It is assumed that the first level of the memorized bit corresponds to the transistor 1. FIG. 1b shows a transistor 1' that possesses a source connected to the ground, a gate connected to a control line 2' and a drain connected to a bit line 3'. Now, the transistor 1' is totally neutralized by the elimination of the active zone under the control gate. When this storage element has to be selected, the control line 2' is positioned at a positive voltage greater than the threshold voltage of a MOS transistor and the bit line 3' remains in a floating state. It is assumed that the second level of the memorized bit corresponds to the transistor 1'. A cell of this kind has the advantage of having high integration capacity and of using standard methods of manufacture. Unfortunately, the programming by "active level" takes place at the second masking level, namely very early in the manufacturing process. This type of programming done very early in the manufacturing cycle gives rise to major delays (of several weeks) in delivery. Accordingly, the capacity of a company to carry out the high-speed production of circuits that are encoded by the customer is considerably reduced.
There also exist "P minus" type ROMs. The storage elements are shown in FIGS. 2a and 2b. Each of the FIGS. 2a and 2b illustrates a possible state of the bit to be memorized. Naturally, the state of the bit is arbitrary and depends on everything that is placed between the transistor acting as a storage element and the output of the memory. FIG. 2a shows a transistor 4 with a source connected to the ground, a gate connected to the control line 5 and a drain connected to a bit line 6. When it is desired to select this storage element, the control line 5 is set at a positive voltage greater than the threshold voltage of a MOS transistor and the bit line 6 gets connected to the ground by means of the transistor 4. The first level of the memorized bit is considered to correspond to the transistor 4. FIG. 2b shows a transistor 4' with a gate connected to a control line 5', a drain connected to a bit line 6 by means of a reverse-mounted diode 7 and a source connected to the ground. The diode is in fact formed by the implantation of a dopant of a type opposite to the doping of the drain. In general, N channel type transistors are used, the implantation being then made with the P type doping in a low concentration, hence the name "P minus". When it is desired to select this storage element, the control line 5' is positioned at a positive voltage greater than the threshold voltage of a MOS transistor and the bit line 6' remains in a floating state. The second level of the memorized bit is considered to correspond to the transistor 4'. The main advantage of this storage element is that the programming of the element takes place in the second-third part of the manufacturing process, thus reducing delays in delivery. Furthermore, the surface area occupied by the storage element is as small as the previously described element. The main disadvantage is the introduction of an additional step into the standard method for the manufacture of CMOS components. Furthermore, the step added is not compatible with all of the existing methods of manufacture.
There also exists "metal/via" type ROM memories. The storage elements are shown in FIGS. 3a and 3b. Each of the FIGS. 3a and 3b illustrates a possible state of the bit to be memorized. Naturally, the state of the bit is arbitrary and depends on all that is placed between the transistor constituting a storage element and the output of the memory. FIG. 3a shows a transistor 8 with a source connected to the ground, a gate connected to a control line 9 and a drain connected to a bit line 10. When it is desired to select this storage element, the control line 9 is positioned at a positive voltage greater than the threshold voltage of a MOS transistor, and the bit line 10 gets connected to the ground by means of the transistor 8. The first level of the memorized bit is considered to correspond to the transistor 8. FIG. 3b shows a transistor 8' with a source connected to the ground, a gate connected to a control line 9' and a drain disconnected from a bit line 10'. When this storage element is to be selected, the control line 9' is positioned at a positive voltage higher than the threshold voltage of a MOS transistor, and the bit line 10' remains in a floating state. It is felt that the first level of the memorized bit corresponds to the transistor 8'. The connection or non-connection of the transistor is done either by means of a via hole with the highest metal layer or by a strap on the highest metal layer. The main advantage is that the programming of the storage element is done in one of the last two steps of manufacture, thus greatly reducing the delivery delays. Unfortunately, a storage element is at least twice as big as the elements described above. This type of element is therefore not suited to uses involving high-level integration.
All these memory cells have the particular feature of differentiating between the two levels of programming of the storage element either by a transistor or by an open circuit. Consequently, the transistors of the different storage elements are parallel-connected. It is therefore necessary to take account of a minimum spacing between each transistor of each storage element.